ITC'02 SOC Test Benchmarks Bibliography

[1]

Erika Cota et al. The Impact of NoC Reuse on the Testing of Core-based Systems. In Proceedings IEEE VLSI Test Symposium (VTS), pages 128-133, Napa, CA, April 2003.

[2]

Erika Cota, Luigi Carro, Flavio Wagner, and Marcelo Lubaszewski. BISTed cores and Test Time Minimization in NOC-based Systems. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), pages 1-6, Napa, CA, April 2003.

[3]

Sandeep Kumar Goel and Erik Jan Marinissen. A Novel Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. In Proceedings IEEE European Test Workshop (ETW), pages 7-12, Corfu, Greece, May 2002.

[4]

Sandeep Kumar Goel and Erik Jan Marinissen. Cluster-Based Test Architecture Design for System-on-Chip. In Proceedings IEEE VLSI Test Symposium (VTS), pages 259-264, Monterey, CA, April 2002.

[5]

Sandeep Kumar Goel and Erik Jan Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529-538, Baltimore, MD, October 2002.

[6]

Sandeep Kumar Goel and Erik Jan Marinissen. Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. In Proceedings Design, Automation, and Test in Europe (DATE), pages 738-743, Munich, Germany, March 2003.

[7]

Huan-Shan Hsu et al. Test Scheduling and Test Access Architecture Optimization for System-on-Chip. In Proceedings IEEE Asian Test Symposium (ATS), pages 411-416, Tamuning, Guam, USA, November 2002.

[8]

Yu Huang et al. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. In Digest of Papers of IEEE European Test Workshop (ETW), pages 35-40, Corfu, Greece, May 2002.

[9]

Yu Huang et al. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. In Proceedings IEEE International Test Conference (ITC), pages 74-82, Baltimore, MD, October 2002.

[10]

Yu Huang, Sudhakar M. Reddy, and Wu-Tung Cheng. Core-Clustering Based SOC Test Scheduling Optimization. In Proceedings IEEE Asian Test Symposium (ATS), pages 405-410, Tamuning, Guam, USA, November 2002.

[11]

Vikram Iyengar and Krishnendu Chakrabarty. Test Bus Sizing for System-on-a-Chip. IEEE Transactions on Computers, 51:449-459, May 2002.

[12]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):213-230, April 2002.

[13]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Efficient Wrapper/TAM Co-Optimization for Large SOCs. In Proceedings Design, Automation, and Test in Europe (DATE), pages 491-498, Paris, France, March 2002.

[14]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 685-690, New Orleans, LO, June 2002.

[15]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. In Proceedings IEEE VLSI Test Symposium (VTS), pages 253-258, Monterey, CA, April 2002.

[16]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Recent Advances in TAM Optimization, Test Scheduling, and Test Resource Management for Modular Testing of Core-Based SOCs. In Proceedings IEEE Asian Test Symposium (ATS), pages 320-325, Guam, USA, November 2002.

[17]

Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Test Resource Optimization for Multi-Site Testing of Embedded-Core-Based SOCs Using ATE With Memory Depth Constraints. In Digest of Papers of IEEE European Test Workshop (ETW), pages 29-34, Corfu, Greece, May 2002.

[18]

Vikram Iyengar, Sandeep Kumar Goel, Krishnendu Chakrabarty, and Erik Jan Marinissen. Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. In Proceedings IEEE International Test Conference (ITC), pages 1159-1168, Baltimore, MD, October 2002.

[19]

Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty. On SOC Test Resource Optimization for Multi-Site Testing Using ATE With Memory Depth Constraints. In Proceedings North-American Test Workshop (NATW), pages 77-83, Montauk, NY, May 2002.

[20]

Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, and Gopind N. Kumar. Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. In Proceedings IEEE VLSI Test Symposium (VTS), pages 299-304, Napa, CA, April 2003.

[21]

Sandeep Koranne and Vikram Iyengar. On the Use of k-tuples for SoC Test Schedule Representation. In Proceedings IEEE International Test Conference (ITC), pages 539-548, Baltimore, MD, October 2002.

[22]

Sandeep Koranne. A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm. Journal of Electronic Testing: Theory and Applications, 18(4/5):415-434, August 2002.

[23]

Sandeep Koranne. A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm, volume 21 of Frontiers in Electronics Testing, pages 51-70. Kluwer Academic Publishers, September 2002.

[24]

Sandeep Koranne. Test Resource Partitioning and Scheduling Using Graph Factoring. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), pages 3.1-1-8, Baltimore, MD, October 2002.

[25]

Chunsheng Liu and Krishnendu Chakrabarty. A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. In Proceedings Design, Automation, and Test in Europe (DATE), pages 230-235, Munich, Germany, March 2003.

[26]

Erik Jan Marinissen and Sandeep Kumar Goel. Analysis of Test Bandwidth Utilization in Test Bus and TestRail Architectures for SOCs. In Proceedings IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), pages 52-60, Brno, Czech Republic, April 2002.

[27]

Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. ITC'02 SOC Test Benchmarks Web Site. http://www.extra.research.philips.com/itc02socbenchm/.

[28]

Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proceedings IEEE International Test Conference (ITC), pages 519-528, Baltimore, MD, October 2002.

[29]

Mohsen Nahvi and Andre Ivanov. An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. In Proceedings IEEE VLSI Test Symposium (VTS), pages 293-298, Napa, CA, April 2003.

[30]

Mohsen Nahvi, Andre Ivanov, and Resve Saleh. Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. In Proceedings IEEE International Test Conference (ITC), pages 1176-1183, Baltimore, MD, October 2002.

[31]

Chih-Ping Su and Cheng-Wen Wu. Graph-Based Power-Constrained Test Scheduling for SOC. In Proceedings IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), pages 61-68, Brno, Czech Republic, April 2002.

[32]

Qiang Xu and Nicola Nicolici. Delay Fault Testing of Core-Based Systems-on-a-Chip. In Proceedings Design, Automation, and Test in Europe (DATE), pages 744-749, Munich, Germany, March 2003.

[33]

Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, and Yu Huang. SOC Test Scheduling Using Simulated Annealing. In Proceedings IEEE VLSI Test Symposium (VTS), pages 325-330, Napa, CA, April 2003.

Erik Jan Marinissen, Philips Research (Erik . Jan . Marinissen @ philips . com)
Last modified on: Tuesday, May 13, 2003