TECS Bibliography

[1]

Jais Abraham et al. Test Methodology Framework for Embedded Core Based Systems. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.4-1-5, Montreal, Canada, May 2000.

[2]

Saman Adham et al. Preliminary Outline of IEEE P1500 Scalable Architecture for Testing Embedded Cores. In Proceedings IEEE VLSI Test Symposium (VTS), pages 483-488, Dana Point, CA, USA, April 1999.

[3]

Advanced RISC Machines Ltd. The ARM7TDMI Debug Architecture, December 1995. ARM DAI 0028A, http://www.arm.com/Documentation/AppNotes/Apps28vA.

[4]

Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, USA, October 1998.

[5]

Joep Aerts. Test Time Reduction Algorithms for Core-Based ICs. Master's thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, April 1998.

[6]

Rob Aitken and Fidel Muradali. Trends in SLI Design and their Effect on Test. In Proceedings IEEE International Test Conference (ITC), pages 628-637, Atlantic City, NJ, USA, September 1999.

[7]

Alexandre M. Amory, Leandro A. Oliveira, and Fernando G. Moraes. Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures. In Proceedings IFIP International Conference on Very Large Scale Integration (VLSI-SOC), pages 174-179, Darmstadt, Germany, December 2003.

[8]

Thomas Anderson. This is Hard Core. Test - The European Test Industry Journal, Vol. 25(No. 5):S-5-6, June 1999.

[9]

David Appelo et al. Full Built-In Self-Test Solution for System-on-Chip. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.2-1-5, Marina del Rey, CA, USA, May 2001.

[10]

Robert Arendsen and Maurice Lousberg. Core Based Test for a System on Chip Architecture Framework. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 5.1-1-8, Washington, DC, USA, October 1998.

[11]

William D. Atwell, William C. Bruce Jr., and Grady L. Giles. Tester On A Chip (TOAC) or Apparatus for Application of Tests for Embedded Test Points. Motorola Technical Developments, Vol. 9:21-25, August 1989.

[12]

Marcel Baláz and Elena Gramatová. Optimization Techniques for Parallel Interface of Test Wrapper for Embedded Cores. In Digest of Papers of IEEE European Test Workshop (ETW), pages 25-26, Maastricht, The Netherlands, May 2003.

[13]

Luis Basto, Asif Khan, and Pete Hodakievic. Embedded X86 Testing Methodology. In Proceedings IEEE International Test Conference (ITC), pages 487-492, Atlantic City, NJ, USA, September 1999.

[14]

Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, and Sudipta Bhawmik. An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. Journal of Electronic Testing: Theory and Applications, 18(4/5):475-485, August 2002.

[15]

Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, and Sudipta Bhawmik. An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. In Krishnendu Chakrabarty, editor, SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, volume 21 of Frontiers in Electronics Testing, pages 111-121. Kluwer Academic Publishers, September 2002.

[16]

Ken Batcher and Christos Papachristou. Instruction Randomization Self Test for Processor Cores. In Proceedings IEEE VLSI Test Symposium (VTS), pages 34-40, Dana Point, CA, USA, April 1999.

[17]

Hakim Bederr and Franck Chirat. At-Speed Test of a DSP Subsystem Embeed in a Wireless Application Chip. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.3-1-11, Dana Point, CA, USA, April 1999.

[18]

Frans Beenker, Karel van Eerdewijk, Robert Gerritsen, Frank Peacock, and Max van der Star. Macro Testing: Unifying IC and Board Test. IEEE Design & Test of Computers, Vol. 3(No. 4):26-32, December 1986.

[19]

Frans Beenker, Rob Dekker, Rudi Stans, and Max van der Star. A Testability Strategy for Silicon Compilers. In Proceedings IEEE International Test Conference (ITC), pages 660-696, September 1989.

[20]

Frans Beenker, Rob Dekker, Rudi Stans, and Max van der Star. Implementing Macro Test in Silicon Compiler Designs. IEEE Design & Test of Computers, Vol. 7(No. 2):41-51, April 1990.

[21]

Frans Beenker, Ben Bennetts, and Loek Thijssen. Testability Concepts for Digital ICs - The Macro Test Approach, volume 3 of Frontiers in Electronics Testing. Kluwer Academic Publishers, Boston, MA, USA, 1995.

[22]

Frans Beenker. Testability Concepts for Digital ICs. PhD thesis, Twente University, Enschede, The Netherlands, April 1994.

[23]

Mounir Benabdenbi, Walid Maroufi, and Meryem Marzouki. CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. In Proceedings Design, Automation, and Test in Europe (DATE), pages 141-145, Paris, France, March 2000.

[24]

Mounir Benabdenbi, Walid Maroufi, and Meryem Marzouki. Testing TAPed Cores and Wrapped Cores With The Same Test Access Mechanism. In Proceedings Design, Automation, and Test in Europe (DATE), pages 150-155, Munich, Germany, March 2001.

[25]

Mounir Benabdenbi, Walid Maroufi, and Meryem Marzouki. CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. Journal of Electronic Testing: Theory and Applications, 18(4/5):455-473, August 2002.

[26]

Mounir Benabdenbi, Walid Maroufi, and Meryem Marzouki. CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. In Krishnendu Chakrabarty, editor, SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, volume 21 of Frontiers in Electronics Testing, pages 91-109. Kluwer Academic Publishers, September 2002.

[27]

M. Benabdenbi, A. Greiner, F. Pecheux, E. Viaud, and M. Tuna. STEPS: Experimenting a New Software-based Strategy for Testing SoCs Containing P1500-compliant IP Cores. In Proceedings Design, Automation, and Test in Europe (DATE), pages 712-713, Paris, France, February 2004.

[28]

Ben Bennetts. A Design Strategy for System-on-a-Chip Testing. Electronic Products, pages 57-59, June 1997.

[29]

Alfredo Benso et al. HD²BIST: A Hierarchical Framework for BIST Scheduling, Data Patterns Delivering and Diagnosis in SoCs. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.3-1-8, Montreal, Canada, May 2000.

[30]

Alfredo Benso et al. HD²BIST: A Hierarchical Framework for BIST Scheduling, Data Patterns Delivering and Diagnosis in SoCs. In Proceedings IEEE International Test Conference (ITC), pages 892-901, Atlantic City, NJ, USA, October 2000.

[31]

A. Benso, G. Borgonovo, D. Grassi, M. Lobetti-Bodoni, and A. Pricco. An Industrial Approach to Core Testing. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.3-1-4, Washington, DC, USA, October 1998.

[32]

A. Benso, S. Chiusano, P. Prinetto, and Y. Zorian. HD-BIST: A Hierarchical Distributed BIST Architecture for System-on-a-Chip. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 2.4-1-5, Washington, DC, USA, October 1998.

[33]

Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, and Yervant Zorian. A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 4.3-1-5, Dana Point, CA, USA, April 1999.

[34]

Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, and Yervant Zorian. HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SOCs. In Proceedings IEEE International Test Conference (ITC), pages 1038-1044, Atlantic City, NJ, USA, September 1999.

[35]

Sandeep Bhatia, Tushar Gheewala, and Prab Varma. A Unifying Methodology for Intellectual Property and Custom Logic Testing. In Proceedings IEEE International Test Conference (ITC), pages 639-648, Washington, DC, USA, October 1996.

[36]

Debashis Bhattacharya. Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. In Proceedings IEEE VLSI Test Symposium (VTS), pages 8-14, Monterey, CA, USA, April 1998.

[37]

Debashis Bhattacharya. Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. In Proceedings IEEE VLSI Test Symposium (VTS), pages 467-472, Dana Point, CA, USA, April 1999.

[38]

A. Bommireddy, J. Khare, S. Shaikh, and S-T. Su. Test and Debug of Networking SoCs - A Case Study. In Proceedings IEEE VLSI Test Symposium (VTS), pages 121-126, Montreal, Canada, April 2000.

[39]

Marcel Boosten and Harro Jacobs. Test Protocol Expansion: Memory Handling and Efficiency Improvements. Master's thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, June 1994.

[40]

Frank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, and Frans Beenker. Macro Testability; The Results of Production Device Applications. In Proceedings IEEE International Test Conference (ITC), pages 232-241, September 1992.

[41]

Hans Bouwmeester, Steven Oostdijk, Frank Bouwman, Rudi Stans, Loek Thijssen, and Frans Beenker. Minimizing Test Time by Exploiting Parallelism in Macro Test. In Proceedings IEEE International Test Conference (ITC), pages 451-460, September 1993.

[42]

Hans Bouwmeester. Reducing the Test Time of VLSI Devices by Exploiting Parallelism in Macro Test. Master's thesis, Delft University of Technology, Delft, The Netherlands, July 1992.

[43]

Andrew Burdass et al. Embedded Test and Debug of Full Custom and Synthesisable Microprocessor Cores. In Proceedings IEEE European Test Workshop (ETW), pages 17-22, Cascais, Portugal, May 2000.

[44]

Andrew Burdass, Gary Campbell, Richard Grisenthwaite, and Richard York. Testing Embedded Synthesizable IP - A Case Study. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.2-1-5, Montreal, Canada, May 2000.

[45]

Krishnendu Chakrabarty and Erik Jan Marinissen. TECS'02 Panel Summary: How Useful Are The ITC'02 SOC Test Benchmarks? IEEE Design & Test of Computers, 19(5):119-120, September 2002.

[46]

Krishnendu Chakrabarty, Rajatish Mukherjee, and Andrew S. Exnicios. Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test. In Proceedings IEEE International Conference on VLSI Design (ICVD), pages 431-436, Bangalore, India, January 2001.

[47]

Krishnendu Chakrabarty. Test Scheduling for Core-Based Systems. In Proceedings International Conference on Computer-Aided Design (ICCAD), pages 391-394, San Jose, CA, USA, November 1999.

[48]

Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 432-437, Los Angeles, CA, USA, June 2000.

[49]

Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, April 2000.

[50]

Krishnendu Chakrabarty. Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming. IEEE Transactions on Computer-Aided Design, 19(10):1163-1174, October 2000.

[51]

Krishnendu Chakrabarty. Optimal Test Access Architectures for System-on-a-Chip. ACM Transactions on Design Automation of Electronic Systems, 6(1):26-49, January 2001.

[52]

Tapan J. Chakraborty, Sudipta Bhawmik, and Chen-Huan Chiang. Test Access Methodology for System-On-Chip Testing. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.1-1-7, Montreal, Canada, May 2000.

[53]

Anshuman Chandra, Sharon Schweizer, Vikram Iyengar, and Krishnendu Chakrabarty. A Unified Approach for SOC Test Resource Partitioning Using Test Data Compression and TAM Optimization. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), pages 4.4-1-7, Baltimore, MD, USA, October 2002.

[54]

R. Chandramouli and Stephen Pateras. Testing Systems on a Chip. IEEE Spectrum, pages 42-47, November 1996.

[55]

Li Chen et al. Embedded Hardware and Software Self-Testing Methodologies for Processor Cores. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 625-630, Los Angeles, CA, USA, June 2000.

[56]

Kuo-Liang Cheng et al. An SOC Test Integration Platform and Its Industrial Realization. In Proceedings IEEE International Test Conference (ITC), pages 1213-1222, Charlotte, NC, USA, October 2004.

[57]

James Chin and Mehrdad Nourani. SOC Test Schedulin With Power-Time Tradeoff and Hot Spot Avoidance. In Proceedings Design, Automation, and Test in Europe (DATE), pages 710-711, Paris, France, February 2004.

[58]

Érika Cota et al. The Impact of NoC Reuse on the Testing of Core-based Systems. In Proceedings IEEE VLSI Test Symposium (VTS), pages 128-133, Napa, CA, USA, April 2003.

[59]

Érika Cota, Luigi Carro, Flávio Wagner, and Marcel Lubaszewski. Power-Aware NoC Reuse on the Testing of Core-Based Systems. In Proceedings IEEE International Test Conference (ITC), pages 612-621, Charlotte, NC, USA, September 2003.

[60]

Érika Cota, Luigi Carro, Flávio Wagner, and Marcelo Lubaszewski. BISTed cores and Test Time Minimization in NOC-based Systems. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), pages 1-6, Napa, CA, USA, April 2003.

[61]

Érika Cota, Luigi Carro, Flávio Wagner, and Marcelo Lubaszewski. Power-Aware NoC Reuse on the Testing of Core-Based Systems. In Digest of Papers of IEEE European Test Workshop (ETW), pages 123-128, Maastricht, The Netherlands, May 2003.

[62]

Erika Cota, Luigi Carro, and Marcelo Lubaszewski. Reusing an On-Chip Network for the Test of Core-Based Systems. ACM Transactions on Design Automation of Electronic Systems, Vol. 9(No. 4):471-499, October 2004.

[63]

Al Crouch and Jeff Freeman. ColdFire Processor is Hot for DfT. Test - The European Test Industry Journal, Vol. 24(No. 6):15-16, July 1998.

[64]

Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, and Rohit Kapur. Overview of the IEEE P1500 Standard. In Proceedings IEEE International Test Conference (ITC), pages 988-997, Charlotte, NC, USA, September 2003.

[65]

Francisco DaSilva, editor. IEEE Std 1500^TM-2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE, New York, NY, USA, August 2005.

[66]

Hiroshi Date, Toshinori Hosokawa, and Michiaki Muraoka. A SoC Test Strategy Based on a Non-Scan DFT Method. In Proceedings IEEE Asian Test Symposium (ATS), pages 305-310, Tamuning, Guam, USA, November 2002.

[67]

Kaushik De. Test Methodology for Embedded Cores which Protects Intellectual Property. In Proceedings IEEE VLSI Test Symposium (VTS), pages 2-9, Monterey, CA, USA, April 1997.

[68]

Bulent Dervisoglu and Janardhana Swamy. A Novel Approach for Designing a Hierarchical Test Access Controller for Embedded Core Designs in an SoC Environment. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.4-1-7, Montreal, Canada, May 2000.

[69]

Bulent Dervisoglu. Designing Hierarchical Test Access Controllers for Embedded Cores using IEEE P1500 and VSIA Compliant Architectures. In Digest of Papers of IEEE European Test Workshop (ETW), pages 101-106, Saltsjobaden, Sweden, May 2001.

[70]

Sujit Dey, Erik Jan Marinissen, and Yervant Zorian. Testing System Chips: Methodologies and Experiences. Integrated System Design, Vol. 11(No. 123):36-48, September 1999.

[71]

O.P. Dias, J. Semiao, I.M. Teixeira, and J.P. Teixeira. Soft Wrapper Design for Embedded Cores Using a System Level Approach. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 4.4-1-7, Dana Point, CA, USA, April 1999.

[72]

Rainer Dorsch, Ramon Huerta Rivera, Hans-Joachim Wunderlich, and Martin Fischer. Adapting an SoC to ATE Concurrent Test Capabilities. In Proceedings IEEE International Test Conference (ITC), pages 1169-1175, Baltimore, MD, USA, October 2002.

[73]

Frank S. Eory. A Core-Based System-to-Silicon Design Methodology. IEEE Design & Test of Computers, 14(4):36-41, December 1997.

[74]

T. Falter and D. Richter. Overview of Status and Challenges of System Testing on Chip with Embedded DRAMs. Solid State Electronics, 44(5):761, 2000.

[75]

Chris Feige and Clemens Wouters. Integration of Structural Test Methods into a Architecture Specific Core-Test Approach. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 5.2-1-8, Washington, DC, USA, October 1998.

[76]

Chris Feige, Jan ten Pierick, Clemens Wouters, Ronald Tangelder, and Hans Kerkhoff. Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach. In Digest of Papers of IEEE European Test Workshop (ETW), Barcelona, Spain, May 1998.

[77]

Chris Feige, Jan ten Pierick, Clemens Wouters, Ronald Tangelder, and Hans G. Kerkhoff. Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach. Journal of Electronic Testing: Theory and Applications, 14(1-2):125-131, February 1999.

[78]

Fabrizio Ferrandi et al. Testing Core-Based Systems: A Symbolic Methodology. IEEE Design & Test of Computers, 14(4):69-77, December 1997.

[79]

Martin Fischer, Ramon Huerta Rivera, Rainer Dorsch, and Hans-Joachim Wunderlich. Adapting an SoC to ATE Concurrent Test Capabilities. In Digest of Papers of IEEE European Test Workshop (ETW), pages 275-280, Corfu, Greece, May 2002.

[80]

Marie-Lise Flottes, Julien Pouget, and Bruno Rouzeyre. Sessionless Test Scheme: Power-Constrained Test Scheduling for System-on-a-Chip. In Proceedings IFIP International Conference on Very Large Scale Integration (VLSI-SOC), pages 105-110, Montpellier, France, December 2001.

[81]

Marie-Lise Flottes, Julien Pouget, and Bruno Rouzeyre. Power-Constrained Test Scheduling for SOCs Under a ``No Session'' Scheme. In Michel Robert, Bruno Rouzeyre, Christian Piguet, and Marie-Lise Flottes, editors, SOC Design Methodologies, pages 401-412. Kluwer Academic Publishers, 2002.

[82]

Patrick Gallagher et al. A Building Block BIST Methodology for SOC Designs: A Case Study. In Proceedings IEEE International Test Conference (ITC), pages 111-120, Baltimore, MD, USA, October 2001.

[83]

Indradeep Ghosh, Niraj K. Jha, and Sujit Dey. A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems. In Proceedings IEEE International Test Conference (ITC), pages 50-59, Washington, DC, USA, November 1997.

[84]

Indradeep Ghosh, Sujit Dey, and Niraj K. Jha. A Fast and Low Cost Testing Technique for Core-based System-on-Chip. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 542-547, San Francisco, CA, USA, June 1998. Association for Computing Machinery, Inc.

[85]

Indradeep Ghosh, Niraj K. Jha, and Sujit Dey. Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems-on-a-Chip. IEEE Transactions on Computer-Aided Design, 18(11):1661, November 1999.

[86]

Indradeep Ghosh, Sujit Dey, and Niraj K. Jha. A Fast and Low-Cost Testing Technique for Core-Based System-Chips. IEEE Transactions on Computer-Aided Design, 19(8):863, August 2000.

[87]

Sandeep Kumar Goel and Erik Jan Marinissen. TAM Architectures and Their Implication on Test Application Time. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.3-1-10, Marina del Rey, CA, USA, May 2001.

[88]

Sandeep Kumar Goel and Erik Jan Marinissen. A Novel Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. In Proceedings IEEE European Test Workshop (ETW), pages 7-12, Corfu, Greece, May 2002.

[89]

Sandeep Kumar Goel and Erik Jan Marinissen. Cluster-Based Test Architecture Design for System-on-Chip. In Proceedings IEEE VLSI Test Symposium (VTS), pages 259-264, Monterey, CA, USA, April 2002.

[90]

Sandeep Kumar Goel and Erik Jan Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529-538, Baltimore, MD, USA, October 2002.

[91]

Sandeep Kumar Goel and Erik Jan Marinissen. A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. Journal of Electronic Testing: Theory and Applications, 19(4):425-435, August 2003.

[92]

Sandeep Kumar Goel and Erik Jan Marinissen. Control-Aware Test Architecture Design for Modular SOC Testing. In Proceedings IEEE European Test Workshop (ETW), pages 57-62, Maastricht, The Netherlands, May 2003.

[93]

Sandeep Kumar Goel and Erik Jan Marinissen. Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. In Proceedings Design, Automation, and Test in Europe (DATE), pages 738-743, Munich, Germany, March 2003.

[94]

Sandeep Kumar Goel and Erik Jan Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4):399-429, October 2003.

[95]

Sandeep Kumar Goel and Erik Jan Marinissen. On-Chip Test Infrastructure Design for High-Throughput Multi-Site Testing of SOCs. In Digest of Papers of IEEE International Infrastructure IP Workshop (IIP), page 1.1, Charlotte, NC, USA, 2004.

[96]

Sandeep Kumar Goel and Erik Jan Marinissen. TR-Architect: DfT and Test Support for SOC Designers. In Proceedings of the IEEE/ProRISC Symposium on Circuits, Systems and Signal Processing, Veldhoven, The Netherlands, November 2004.

[97]

Sandeep Kumar Goel and Erik Jan Marinissen. On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. In Proceedings Design, Automation, and Test in Europe (DATE), pages 44-49, Munich, Germany, March 2005.

[98]

Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk. Test Infrastructure Design for the Nexperia^TM Home Platform PNX8550 System Chip. In Proceedings Design, Automation, and Test in Europe (DATE) Designers Forum, pages 108-113, Paris, France, February 2004.

[99]

Sandeep Kumar Goel. Test Access Planning for Embedded Core-Based System ICs. Master's thesis, Indian Institute of Technology Delhi, New Delhi, India, December 1999.

[100]

Sandeep Kumar Goel. A Novel Wrapper Cell Design for Efficient Testing of Hierarchical Cores in System Chips. In Digest of Papers of IEEE European Test Symposium (ETS), pages 147-152, Ajaccio, Corsica, France, May 2004.

[101]

M. Goessel, E.S. Sogomonyan, and A. Morosov. A New Totally Error Propagating Compactor for Arbitrary Cores With Digital Interfaces. In Proceedings IEEE VLSI Test Symposium (VTS), pages 49-56, Dana Point, CA, USA, April 1999.

[102]

Paul T. Gonciari, Bashir M. Al-Hashimi, and Nicola Nicolici. Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. In Proceedings IEEE International Test Conference (ITC), pages 64-73, Baltimore, MD, USA, October 2002.

[103]

Paul T. Gonciari, Bashir M. Al-Hashimi, and Nicola Nicolici. Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. In Proceedings IEEE VLSI Test Symposium (VTS), pages 423-429, Monterey, CA, USA, April 2002.

[104]

Liam Goudge. Debugging Embedded Systems. http://www.arm.com/Documentation/WhitePapers/DebugEmbSys, 1998.

[105]

Bruce S. Greene and Samiha Mourad. Accessing Cores through Scan Path Chains. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 4.2-1-4, Dana Point, CA, USA, April 1999.

[106]

Kevin M. Grosselfinger and James A. Monzel. A Production Test Environment for Complex System On a Chip ASIC Products Incorporating the Rambus ASIC Cell. In Digest of Papers of IEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 3.3-1-6, Washington, DC, USA, October 1998.

[107]

Rajesh K. Gupta and Yervant Zorian. Introducing Core-Based System Design. IEEE Design & Test of Computers, 14(4):15-25, December 1997.

[108]

Alan Hales and Erik Jan Marinissen. IEEE P1500 Web Site. http://grouper.ieee.org/groups/1500/.

[109]

Peter Harrod. Testing Reusable IP - A Case Study. In Proceedings IEEE International Test Conference (ITC), pages 493-498, Atlantic City, NJ, USA, September 1999.

[110]

Shankar Hemmady, Tom Anderson, and Yervant Zorian. Verification and Testing of Embedded Cores. In Proceedings of Design SuperCon, pages S122-1-19, January 1997.

[111]

Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, and Zainalabedin Navabi. A Concurrent Testing Method for NoC Switches. In Proceedings Design, Automation, and Test in Europe (DATE), pages 1-6, Munich, Germany, March 2006.

[112]

Huan-Shan Hsu et al. Test Scheduling and Test Access Architecture Optimization for System-on-Chip. In Proceedings IEEE Asian Test Symposium (ATS), pages 411-416, Tamuning, Guam, USA, November 2002.

[113]

Yu Huang et al. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. In Proceedings IEEE Asian Test Symposium (ATS), pages 265-270, Kyoto, Japan, November 2001.

[114]

Yu Huang et al. Constraint-Driven Pin Mapping for Concurrent SOC Testing. In Proceedings IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Bangelore, India, January 2002.

[115]

Yu Huang et al. On Concurrent Test of Core-Based SOC Design. Journal of Electronic Testing: Theory and Applications, 18(4/5):401-414, August 2002.

[116]

Yu Huang et al. On Concurrent Test of Core-Based SOC Design. In Krishnendu Chakrabarty, editor, SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, volume 21 of Frontiers in Electronics Testing, pages 37-50. Kluwer Academic Publishers, September 2002.

[117]

Yu Huang et al. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. In Digest of Papers of IEEE European Test Workshop (ETW), pages 35-40, Corfu, Greece, May 2002.

[118]

Yu Huang et al. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. In Proceedings IEEE International Test Conference (ITC), pages 74-82, Baltimore, MD, USA, October 2002.

[119]

Jing-Reng Huang, Madhu K. Iyer, and Kwang-Ting Cheng. A Self-Test Methodology for IP Cores in Bus-Based Programmable SOCs. In Proceedings IEEE VLSI Test Symposium (VTS), pages 198-203, Marina del Rey, CA, USA, May 2001.

[120]

Yu Huang, Sudhakar M. Reddy, and Wu-Tung Cheng. Core-Clustering Based SOC Test Scheduling Optimization. In Proceedings IEEE Asian Test Symposium (ATS), pages 405-410, Tamuning, Guam, USA, November 2002.

[121]

Paul Hughes, Peter Harrod, and Gary Campbell. Embedded CPU Test Strategies. In Digest of Papers of IEEE European Test Workshop (ETW), pages 281-285, Corfu, Greece, May 2002.

[122]

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Erik Jan Marinissen, Philips Research (Erik . Jan . Marinissen @ philips . com)
Last modified on: Friday, August 22, 2008