Benchmark Naming

We have adopted a naming scheme for the benchmark SOCs with 'useful' benchmark names. The names assigned to the benchmark SOCs consist of one letter, followed by a number.

Letter

The letter represents the origin of the benchmark. Letters have been (and continue to will be) given out to benchmark contributors on a first-come-first-serve basis. This naming scheme is not guaranteed to be conflict free, but we resolve name conflicts in an ad-hoc manner whenever they occur. Three letters have a 'reserved meaning'.

We are not using the letters 'c' and 's', in order to avoid confusion with the well-known ISCAS'85 and ISCAS'89 benchmark circuits.
The letter 'x' is reserved for SOC benchmark contributors who want to remain anonymous.

Letters given out so far are the following.

a: Analog Devices, Austin, TX, U.S.A.
d: Duke University, Durham, NC, U.S.A.
f: Faraday Technologies, Hsinchu, Taiwan
g: Jiri Gaisler and University of Stuttgart, Stuttgart, Germany
h: National Tsing Hua University, Hsinchu, Taiwan
p: Philips Electronics, Eindhoven, The Netherlands
q: Hewlett-Packard, Shrewsbury, MA, U.S.A.
t: Texas Instruments, Bangalore, India
u: Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil

Number

The subsequent number is a positive integer, meant to give an indication of the test complexity of the SOC. The number is calculated based on a formula first published in [Iyengar et al. - ITC'01]. Let T be the set of module tests. For Test t in T and corresponding Module m(t), the formula uses the numbers of primary inputs i_m(t), primary outputs o_m(t), bidirectional terminals b_m(t), scan chains s_m(t), internal scan chain lengths l_m(t),1, l_m(t),2 , ..., l_{m(t),s_m(t)}, the binary parameters for ScanUse su_t and TamUse tu_t, and the test pattern count p_t. The formula that calculates the SOC number is as follows.

The scaling factor 1/10,000 is used to shorten the (often large) SOC test complexity number obtained from the formula, in order to make it easier to use.

Benchmark Format

The benchmark format contains the following information per SOC.

The SOC name according to the naming convention described here.
The total number of modules in the SOC.
Global settings that specify whether or not the optional data for layout position and power dissipation are provided.
Per module in the SOC:
- The level in the design hierarchy.
- The number of input, output, and bidirectional terminals.
- The number of scan chains and their lengths.
- The absolute layout location of the core (optional).
- The total number of tests.
- Per test:
  - Whether or not this test uses the core-internal scan chains and/or the core-external TAM.
  - The number of test patterns.
  - The power dissipation (optional).

This page describes the benchmark format in detail. First, we explain how a multi-level design hierarchy is expressed in the benchmark format. Subsequently, we give a short description of all keywords used in the benchmark format. Finally, we illustrate the format by means of an example SOC.

SOC Design Hierarchy

Our SOC benchmark format supports the description of multiple levels of design hierarchy. We can describe the embedding of cores within cores. The format also supports SOC design in which only some pre-designed cores are used, and the remaining SOC circuitry is interconnect wiring, glue logic, and/or user-defined blocks.

A uniform description of the SOC hierarchy is enabled by using the term 'Module' to denote each SOC component that is tested as a stand-alone unit. The SOC itself, i.e., the top-level design unit, is a module. It contains the non-core circuitry. Other modules are embedded in this top-level model. These modules can be pre-designed embedded cores, but also user-defined modules, of which the circuit structure and/or size justify stand-alone testing. And these modules can in their turn contain again other modules, etc.

In order to express the design hierarchy in the benchmark format, we use the keywords Module and Level. Modules are numbered in sequence, starting with 'Module 0', which always represents the top-level SOC design. The levels are also numbered in sequence and indicate the level of a particular module in the design hierarchy tree. 'Module 0' has by definition 'Level 0', whereas a module embedded in a module of 'Level n' has 'Level n+1'.

Figure 1(a) shows an example modular SOC design, containing seven modules. The corresponding design hierarchy tree, consisting of four levels, is shown in Figure 1(b).

Figure 1: Example modular SOC design (a) and the corresponding module hierarchy tree (b).

Keywords

The benchmark format uses keywords with the following meaning.

SocName: Uniquely identifying name of the SOC, determined from the description here.
TotalModules: Total number of modules in this SOC. (A module is either the SOC itself or an embedded core.)
Options: The benchmark format contains both mandatory and optional data. The optional data is XY and Power. If for a certain type of optional data the value '0' is listed here, this means that none of the modules of the SOC has this optional data provided. In case the value '1' is listed, it means that for some or all modules, this data is specified.

For each module, the following information is specified.

Module: Module number. The SOC itself is Module 0.
Level: The level of this module in the SOC design hierarchy. Level 0 refers to the top of the design hierarchy. If a Module M has Level n (for n > 0), this means that M is embedded in the module of level n-1 listed closest above M in the benchmark description.
Inputs, Outputs, Bidirs: The numbers of input-only, output-only, and bidirectional terminals of the module.
ScanChains N : l₁, l₂, ..., l₂: The number N of scan chains of this module, and the lengths l_i, in scan flip flops, of these N scan chains. In case the module has no scan chains, the format is: ScanChains 0 :.
X,Y: The X,Y-coordinate of the center of a core on the SOC layout. X,Y-coordinates are expressed as non-negative integers. The unit and the (0,0) origin of the coordinates are not specified; however, they should be the same for all modules throughout one SOC benchmark. The fact that all X,Y-coordinates should be non-negative integers, means that the (0,0) origin cannot be located inside the SOC die itself. For modules in a design hierarchy, the absolute X,Y-coordinates on the SOC layout are mentioned, not the relative ones. This information is optional. It can be omitted for individual or for all modules of the SOC. In case X,Y-coordinates are not specified for an individual core, they are listed as '-1'.
TotalTests: The number of separate tests for the module.

Per test, the following is listed.

Test: The test number for this module. Numbering starts at 1 and ends at TotalTests.
ScanUse: This is a binary variable (0/1), that specifies whether or not this test uses the core-internal scan chains. If '0', the core-internal scan chains are not used; if '1', the core-internal scan chains are used. It is mandatory to specify this parameter (even though it has no meaning in case the module has no internal scan chains). The setting of this parameter typically influences the number of clock cycles needed to apply one test pattern.
TamUse: This is a binary variable (0/1), that specifies whether or not this test uses a core-external Test Access Mechanism (TAM). If '0', such a TAM is not used; if '1', a TAM is used. It is mandatory to specify this parameter. For tests for which the stimuli are generated outside the module-under-test and/or the responses are observed outside the module-under-test, a TAM is utilized during the test for transportation of stimuli and responses. This is typically the case for external testing (from an ATE), and also for BIST (Built-In Self Test) for which the BIST engine resides outside the module-under-test. For Built-In Self Test (BIST), for which the BIST engine resides inside the core, typically an external TAM is not utilized during the execution of the BIST. In such cases, the TAM bandwidth might be utilized to test another core.
Patterns: The number of test patterns for this test. One test pattern is defined as one coherent set of stimuli and corresponding responses. For scan testing, one test pattern includes a full load, apply, and unload of the scan chains involved.
Power: Power dissipation per test. Power is expressed as a non-negative integer. The unit of power is not specified, but should be the same for all modules throughout one SOC benchmark. This information is optional. It can be omitted for individual or for all modules of the SOC. In case power values are not specified for an individual core test, they are listed as '-1'.

Example

We illustrate the benchmark format by means of an example SOC, named x1331.

x1331.soc

Line 01: SocName x1331
Line 02: TotalModules 7
Line 03: Options Power 1 XY 1

Line 04: Module 0 Level 0 Inputs 312 Outputs 312 Bidirs 0 ScanChains 2 : 54 43
Line 05: Module 0 X -1 Y -1
Line 06: Module 0 TotalTests 2
Line 07: Module 0 Test 1 ScanUse 1 TamUse 1 Patterns 43 Power 128
Line 08: Module 0 Test 2 ScanUse 1 TamUse 1 Patterns 32 Power 537

Line 09: Module 1 Level 1 Inputs 10 Outputs 11 Bidirs 12 ScanChains 4 : 20 21 22 23
Line 10: Module 1 X 678 Y 123
Line 11: Module 1 TotalTests 3
Line 12: Module 1 Test 1 ScanUse 1 TamUse 1 Patterns 567 Power 576
Line 13: Module 1 Test 2 ScanUse 1 TamUse 1 Patterns 876 Power 275
Line 14: Module 1 Test 3 ScanUse 1 TamUse 1 Patterns 908 Power 123

Line 15: Module 2 Level 1 Inputs 44 Outputs 46 Bidirs 0 ScanChains 1 : 100
Line 16: Module 2 X 324 Y 98
Line 17: Module 2 TotalTests 2
Line 18: Module 2 Test 1 ScanUse 1 TamUse 1 Patterns 4356 Power 1334
Line 19: Module 2 Test 2 ScanUse 1 TamUse 1 Patterns 56 Power 2245

Line 20: Module 3 Level 2 Inputs 312 Outputs 312 Bidirs 0 ScanChains 2 : 75 75
Line 21: Module 3 X 304 Y 80
Line 22: Module 3 TotalTests 1
Line 23: Module 3 Test 1 ScanUse 1 TamUse 1 Patterns 25 Power -1

Line 24: Module 4 Level 3 Inputs 112 Outputs 543 Bidirs 23 ScanChains 0 :
Line 25: Module 4 X -1 Y -1
Line 26: Module 4 TotalTests 1
Line 27: Module 4 Test 1 ScanUse 1 TamUse 0 Patterns 12 Power -1

Line 28: Module 5 Level 2 Inputs 312 Outputs 312 Bidirs 0 ScanChains 2 : 75 75
Line 29: Module 5 X 344 Y 80
Line 30: Module 5 TotalTests 1
Line 31: Module 5 Test 1 ScanUse 1 TamUse 1 Patterns 25 Power -1

Line 32: Module 6 Level 3 Inputs 112 Outputs 543 Bidirs 23 ScanChains 0 :
Line 33: Module 6 X -1 Y -1
Line 34: Module 6 TotalTests 1
Line 35: Module 6 Test 1 ScanUse 1 TamUse 0 Patterns 12 Power -1

The example x1331.soc has 35 lines with text and some blank lines. Please note that the line numbers are not part of the format, but are added here for explanation purposes only. The benchmark format allows to insert blank lines; typically, this will be used to distinguish between the various module descriptions.

The first three lines provide general information for this SOC. Line 1 says that the SOC name is 'x1331'. Line 2 specifies that the total number of modules in this SOC is seven. Options in Line 3 lists whether power and layout co-ordinate values for modules are supplied for this benchmark SOC. Both options are listed as '1', which means that both X,Y layout coordinates and power dissipation values are specified.

The next 33 lines describe the seven modules in the SOC. Lines 4-8 describe Module 0. Module 0 has Level 0, which means that Module 0 is the top-level module. This is in fact always the case for Module 0. Module 0 has 312 inputs, 312 outputs, and 0 bidirectional terminals. It contains two scan chains, of lengths 54 and 43 scan flip flops, respectively. Line 5 shows that no X,Y layout coordinates are specified for Module 0. Module 0 has two tests. Test 1 uses both its scan chains, as well as a TAM. The scan chains that are referred to here are the two scan chains of Module 0 itself, as specified in Line 4. Test 1 has 43 test patterns and dissipates 128 units of power. Test 2 of Module 0 uses both its scan chains, as well as a TAM. It has 32 test patterns and dissipates 537 units of power.

Lines 9-14 describe Module 1. Its level is 1, which means that Module 1 is embedded within Module 0. Module 1 has 10 inputs, 11 outputs, and 12 bidirectional terminals. Module 1 has four scan chains, of 20, 21, 22, and 23 scan flip flops long respectively. The X co-ordinate is given as 678 units and the Y co-ordinate is given as 123 units. Module 1 has three tests; all three use both the core-internal scan chains and a TAM. Test 1 has 567 test patterns, and dissipates 576 units of power. Test 2 has 876 test patterns, and dissipates 275 units of power. Test 3 has 908 test patterns, and dissipates 123 units of power.

Modules 2 till 6 are described in the sequel of the example. Modules 4 and 6 do not contain scan chains. Therefore, the parameter ScanUse becomes irrelevant for their tests. The tests of these modules also do not use a TAM, as their parameter TamUse is specified as '0'. Modules 4 and 6 are probably non-logic cores that are tested by means of an internal BIST.

From the order in which the modules of x1331 are specified and their level information, we can establish that the design hierarchy of x1331 is as depicted in Figure 1. Careful inspection of the example SOC shows that Module 3, containing Module 4, has the same properties as Module 5, containing Module 6. This might be due to the fact that Modules 3 and 5 are equal, or, in other words, that Module 2 contains two instances of the same core (although this is not guaranteed by the benchmark format).

Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty - June 25, 2002